pa09 ? PA09A pa09u 1 pa09, PA09A features ? power mos technology 2a peak rating ? high gain bandwidth product 150mhz ? very fast slew rate 200v/s ? protected output stage thermal shutoff ? excellent linearity class a/b output ? wide supply range 12v to 40v ? low bias current, low noise fet input applications ? video distribution and and amplification ? high speed deflection circuits ? power transducers to 2mhz ? coaxial line drivers ? power led or laser diode excitation description the pa09 is a high voltage, high output current operational amplifer optimized to drive a variety of loads from dc through the video frequency range. excellent input accuracy is achieved with a dual monolithic fet input transistor which is cascoded by two high voltage transistors to provide outstanding common mode characteristics. all internal current and voltage levels are referenced to a zener diode biased on by a current source. as a result, the pa09 exhibits superior dc and ac stability over a wide supply and temperature range. high speed and freedom from second breakdown is assured by a complementary power mos output stage. for optimum linearity, especially at low levels, the power mos transistors are biased in the class a/b mode. thermal shutoff provides full protection against overheating and limits the heatsink requirements to dissipate the internal power losses under normal operating conditions. a built-in current limit protects the amplifer against overloading. transient inductive load kickback protection is provided by two internal clamping diodes. external phase compensation allows the user maximum fexibility in obtaining the optimum slew rate and gain bandwidth product at all gain settings. for continuous operation under load, a heatsink of proper rating is recommended. this hybrid integrated circuit utilizes thick flm (cermet) resis - tors, ceramic capacitors and silicon semiconductor chips to maximize reliability, minimize size and give top performance. ultrasonically bonded aluminum wires provide reliable inter - connections at all operating temperatures. the ce, 8-pin to-3 package is hermeti - cally sealed and elec - trically isolated. the use of com-pressible thermal washers and/ or improper mount - ing torque will void the product warranty. please see general operating consider - ations. +37v C37v 470pf r f 100 r s .5 r d 3.9k c f pa09 v i 4 3 7 8 1 c c 5pf di dt = 2a/s i = v i /r s l y 13h 1 5 6 figure 1. pa09 as deflection amplifier deflection amplifier (figure 1) the defection amplifer circuit of figure 1 achieves arbi - trary beam positioning for a fast heads-up display. maximum transition times are 4s while delivering 2a pk currents to the 13mh coil. the key to this circuit is the sense resistor (r s ) which converts yoke current to voltage for op amp feedback. this negative feedback forces the coil current to stay exactly proportional to the control voltage. the network consisting of r d , r f and c f serves to shift from a current feedback via r s to a direct voltage feedback at high frequencies. this removes the extra phase shift caused by the inductor thus preventing oscillation. see application note 5 for details of this and other precision magnetic defection circuit s. equivalent schematic external connections 3 6 2 7 8 5 4 1 q1 q5 q2 d1 d2 q18 q15 q10 q12b q9 c2 q8 q12a q4 q3 c1 q6 q13 q11 q14 d3 q16 q17 q7 q19 top view 1 2 3 4 5 6 7 8 c c Cv s +in Cin +v s out bal c c r c r s = (|+v s | + |Cv s |) r t /1.6 note: input offset voltage trim optional. r t = 10k max r t r s 8-pin to-3 package style ce power operational amplifier pa09 ? PA09A p r o d u c t i n n o v a t i o n f r o m copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com may 2009 apex ? pa09urevm p r o d u c t i n n o v a t i o n f r o m
pa09 ? PA09A 2 pa09u specifications absolute maximum ratings supp ly v ol tage , +v s to C v s 80v output current , within soa 5a po wer dissi pation , internal 1 78w input v ol tage , differential 40v input v ol tage , common mode v s t emperature , pin solder - 10s 300c t emperature, junction 1 150c t emperature range , storage C65 to +150c o perating temperature range, case C55 to +125c pa09 PA09A parameter test conditions 2 min typ max min typ max units input offset v ol tage , initial .5 3 .25 .5 mv offset v ol tage , vs. temperature full temperature range 10 30 5 10 v/c offset v ol tage , vs. supply 10 * v/v bi as current , initial 5 100 3 20 pa bi as current , vs. supply .01 * pa/v offset current , initial 2.5 50 1.5 10 pa input i mpedance, dc 10 11 * input capaci tance 6 * pf common mode v ol tage range 3 full temperature range v s C10 v s C8 * * v common mode rejection, dc full temperature range, v cm = 20v 104 * db gain open l oop gain at 15hz r l = 1k 80 98 * db g ain band width product at 1mhz c c = 5pf 150 * mhz po wer band width r l = 15, c c = 5pf 750 * khz po wer band width r l = 15, c c = 100pf 150 * khz output vo l tage swing 3 full temperature range, i o = 2a v s C8 v s C7 * * v current , peak 4.5 * a settling time to 1% 4v step, c c = 100pf .75 * s settling time to .1% 4v step, c c = 100pf 1.3 * s slew rate c c = 5pf 220 * v/s slew rate c c = 100pf 25 * v/s resi stance 7.5 * power supply vo l tage full temperature range 12 35 40 * * * v current , quiescent 70 85 * * ma thermal resi stance , ac junction to case 4 full temperature range, f > 60hz 1.2 1.3 * * c/w resi stance , dc junction to case full temperature range, f < 60hz 1.6 1.8 * * c/w resi stance , junction to air full temperature range 30 * c/w t emperature range , case meets full range specifcations C25 25 + 85 * * * c the internal substrate contains beryllia (beo). do not break the seal. i f accidentally broken, do not crush, machine, or subject to temperatures in excess of 850c to avoid generating toxic fumes. caution notes: * the specifcation of PA09A is identical to the specifcation for pa09 in applicable column to the left. 1. l ong term operation at the maximum junction temperature will result in reduced product life. derate power dissipation to achieve high mttf. 2. unless otherwise noted: t c = 25c, supply voltage = 35 v . 3. +v s and -v s denote the positive and negative supply rail respectively. total v s is measured from + v s to C v s . 4. rating applies if the output current alternates between both output transistors at a rate faster than 60hz. p r o d u c t i n n o v a t i o n f r o m
pa09 ? PA09A pa09u 3 0 25 50 75 100 125 case temperature, t c (c) 10 40 60 80 power derating internal power dissipation, p (w) C55 100 4 8 9 current limit 6 3 10 100 10k 1m frequency, f (hz) input noise voltage, v n (nv/hz) 1 3 5 8 10 output voltage swing 7 9 100k common mode voltage common mode voltage, v cm (v pp ) 1k 10m frequency, f (hz) common mode rejection common mode rejection, cmr (db) 40 80 120 10k 100k 1k frequency, f(hz) power supply rejection power supply rejection, psr (db) current limit, i lim (a) 15 input noise 1k 10 15 20 C25 25 50 75 7 50 150 70 output current, i o (a) voltage drop from supply (v) 1m 20 60 100 10k 100k 1m 100m 0 20 40 60 80 100 5 junction temperature, t j (c) 4 6 30 300k 1m 3m 10m 30m 20 30 40 50 70 0 100m 10 2 1 125 2 3 4 5 10m 7 5 3 100k 7 30 20 0 | +v s | + | Cv s | = 80v c c = 100pf frequency, f (hz) 0 v/s gain high 300 100 30 10 3 1 1k 300 100 3 1 30 10 gain and slew rate, (v/s) slew rate vs. comp. 1000 compensation capacitor, c c (pf) low 100 80 60 40 20 0 -20 100m 10m 1m 100k 100 10 10k 1k 5pf 33pf 100pf 15pf frequency, f (hz) open loop gain, a (db) small signal response 0 -40 -80 -120 -160 -200 100m 10m 1m 100k 100 10 10k 1k frequency, f (hz) open loop phase, () phase response 5pf 33pf 100pf 330pf 15pf all others 330pf 6.2pf 33pf 100pf 330pf 15pf 60 50 40 30 20 10 1m 3k 1k 30 10 300 100 frequency, f (khz) output voltage, v o (v pp ) power response 90 80 70 100 330pf 30 60 80 total supply voltage, v s (v) 1.4 quiescent current 1.2 40 50 70 .6 .8 normalized quiescent current, i q (x) 1.0 1.6 p r o d u c t i n n o v a t i o n f r o m
pa09 ? PA09A 4 pa09u general please read application note 1 "general operating con - siderations" which covers stability, supplies, heat sinking, mounting, current limit, soa interpretation, and specifcation interpretation. v isit www.cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit; heat sink selection; apex precision powers complete application notes library; technical seminar w orkbook; and evaluation kits. supply voltage the specifed voltage ( v s ) applies for a dual () supply having equal voltages. a nonsymmetrical (ie. +70/C10 v ) or a single supply (ie. 80 v ) may be used as long as the total volt- age between the + v s and C v s rails does not exceed the sum of the voltages of the specifed dual supply. safe operating area (soa) the mosfet output stage of this power operational ampli - fer has two distinct limitations: 1. the current handling capability of the mosfet geometry and the wire bonds. 2. the junction temperature of the output mosfets. safe operating area curves the soa curves combine the effect of these limits and allow for internal thermal delays. for a given application, the direc - tion and magnitude of the output current should be calculated or measured and checked against the soa curves. this is simple for resistive loads but more complex for reactive and emf generating loads. the following guidelines may save extensive analytical efforts: 1. capacitive and inductive loads up to the following maximums are safe: v s capacitive load inductive load 40 v .1f 11mh 30 v 500f 24mh 20 v 2500f 75mh 15 v 100mh 2. short circuits to ground are safe with dual supplies up to 20v . 3. the output stage is protected against transient fyback. however, for protection against sustained, high energy fyback, external fast-recovery diodes should be used. bypassing of supplies each supply rail must be bypassed to common with a tanta - lum capacitor of at least 47f in parallel with a .47f ceramic capacitor directly connected from the power supply pins to the ground plane. output leads keep the output leads as short as possible. i n the video frequency range, even a few inches of wire have signifcant inductance, raising the interconnection impedance and limit - ing the output current slew rate. furthermore, the skin effect increases the resistance of heavy wires at high frequencies. multistrand litz w ire is recommended to carry large video currents with low losses. grounding single point grounding of the input resistors and the input signal to a common ground plane will prevent undesired cur - rent feedback, which can cause large errors and/or instabilities. "single point" is a key phrase here; a ground plane should be used as shielding rather than a current path. l eaving the case of the pa09 foating will cause oscillations in some applications. compensation the pa09 is extremely fexible in terms of choice of compen - sation capacitor for any given gain. the most common ranges are shown in the compensat i on typical performance graph. swinging closer to the supply rails, heavier loads, faster input signal rise and fall times and higher supply voltages all tend to demand larger values of compensation capacitor. this capaci - tor must be rated at least as high as the total voltage applied to the amplifer. i n making specifc value choices, use the square wave stability test presented in app li cati on note 19, figures 40 and 41. i n addition to small signal testing, if the application includes step functions in the input signal, use this circuit to measure large signal response. by increasing square wave amplitude to the maximum of the application, this test may show signifcant distortion of the output waveform following the square wave transitions. i n this case the faster input stages of the pa09 are out-running the output stage and overload recovery time creates the distortion. this speed relationship is also why slew rate does not increase for compensation values below about 27pf. supply current w hen swinging large signals, the output stage of the pa09 demands extra supply current. the following graphs illustrate this current for several conditions for both sine and square wave signals. current is exclusive of any load current and will affect both supply rating and thermal ratings. w hen calculat - ing internal power dissipation, multiply this current times total supply voltage. note that swinging closer to the supply rail demands more 30 50 80 20 40 2.0 5.0 15 3.0 4.0 1.5 2.5 3.5 60 70 25 35 internal voltage drop supply to output v s Cv o (v) output current from +v s or Cv s (a) t c = 25c t = 100ms steady state t = 300ms soa p r o d u c t i n n o v a t i o n f r o m
pa09 ? PA09A pa09u 5 current. output voltage is given as peak. currents are aver - age responding supply readings, but ac monitoring will reveal current pulses corresponding to periods of high slew rate. for example, driving 30 v outputs at 500khz on 40v supplies produces a .8a pulse during negative slew and a 1.2a pulse during positive slew. i f the input signal is over driven by several times the output swing capability, pulses up to 4a may be seen. thermal shutdown protection the thermal protection circuit shuts off the amplifer when the substrate temperature exceeds approximately 150c. this allows heatsink selection to be based on normal operating conditions while protecting the amplifer against excessive junction temperature during temporary fault conditions. thermal protection is a fairly slow-acting circuit and therefore 15v o /23v s 32v o /40v s 15v o /40v s 7.0 5.5 4.0 2.5 1.0 1m 10k 100k normalized i q , (x) quiescent vs. square drive frequency, f (khz) 15v o /23v s 32v o /40v s 15v o /40v s 1.5 1.4 1.3 1.2 1.1 1.0 1000 100 300 normalized i q , (x) quiescent vs. sine drive frequency, f (khz) does not protect the amplifer against transient soa violations (areas outside of the t c = 25c boundary). i t is designed to protect against short-term fault conditions that result in high power dissipation within the amplifer, i f the conditions that cause thermal shutdown are not removed, the amplifer will oscillate in and out of shutdown. this will result in high peak power stresses, destroy signal integrity, and reduce the reli - ability of the device. stability due to its large bandwidth the pa09 is more likely to oscillate than lower bandwidth power operational amplifers. to prevent oscillations a reasonable phase margin must be maintained by: 1. pay very careful attention to supply bypassing and circuit grounding. this is very important when step functions are driven and the pa09 shares supplies with more active devices. 2. keeping the external sumpoint stray capacitance to ground at a minimum and the sumpoint load resistance (input and feedback resistors in parallel) below 500. l arger sumpoint load resistances can be used with increased phase com - pensation and/or bypassing of the feedback resistor. 3. connect the case to a local ac ground potential. current limit i nternal current limiting is provided in the pa09. note the current limit curve given under typical performance graphs is based on junction temperature. i f the amplifer is operated at cold junction temperatures, current limit could be as high as 8 amps. this is above the maximum allowed current on the soa curve of 5 amps. systems using this part must be designed to keep the maximum output current to less than 5 amps under all conditions. the internal current limit only provides this protec - tion for junction temperatures of 80c and above. p r o d u c t i n n o v a t i o n f r o m
pa09 ? PA09A 6 pa09u cont acting cirrus logic support for all apex precision power product questions and inquiries, call toll free 800-546-2739 in north america. for inquiries via email, please contact apex.support@cirrus.com. international customers can also request support by contacting their local cirrus logic sales representative. to fnd the one nearest to you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnifcation, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives con - sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop - erty or environmental damage (critical applications). cirrus products are not designed, authorized or warranted to be suitable for use in products surgically implanted into the body, automotive safety or security devices, life support prod - ucts or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the cus - tomers risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customers customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs, apex precision power, apex and the apex precision power logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. p r o d u c t i n n o v a t i o n f r o m
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